 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| IS43R16160A 16Meg x 16 256-MBIT DDR SDRAM FEATURES ISSI DEVICE OVERVIEW (R) PRELIMINARY INFORMATION NOVEMBER 2005 * * * * * * * * * * * * * * * * * * * Clock Frequency: 200, 166 MHz Power supply (VDD and VDDQ) DDR 333: 2.5V + 0.2V DDR 400: 2.6V + 0.1V SSTL 2 interface Four internal banks to hide row Pre-charge and Active operations Commands and addresses register on positive clock edges (CK) Bi-directional Data Strobe signal for data capture Differential clock inputs (CK and CK) for two data accesses per clock cycle Data Mask feature for Writes supported DLL aligns data I/O and Data Strobe transitions with clock inputs Half-strength and Full-strength drive strength options Programmable burst length for Read and Write operations Programmable CAS Latency (2, 2.5, or 3 clocks) Programmable burst sequence: sequential or interleaved Burst concatenation and truncation supported for maximum data throughput Auto Pre-charge option for each Read or Write burst 8192 refresh cycles every 64ms Auto Refresh and Self Refresh Modes Pre-charge Power Down and Active Power Down Modes Lead-free available ISSI's 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 16-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CK. Commands are registered on the positive edges of CK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable (CKE) and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL 2. KEY TIMING PARAMETERS Parameter Clock Cycle Time CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 -5 DDR400 5 6 7.5 200 166 133 -6 DDR333 6 6 7.5 166 166 133 ns ns ns MHz MHz MHz Unit Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 1 IS43R16160A PIN CONFIGURATIONS 66 pin TSOP - Type II for x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS ISSI (R) PIN DESCRIPTIONS A0-A12 A0-A8 BA0, BA1 DQ0 to DQ15 CK, CK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDM, UDM LDQS, UDQS VDD Vss VDDQ VssQ VREF NC Write Enable x16 Input Mask Data Strobe Power Ground Power Supply for I/O Pin Ground for I/O Pin Input Reference Voltage No Connection 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A PIN FUNCTIONS Symbol A0-A12 Type Input Pin ISSI (R) BA0, BA1 Input Pin CAS CKE Input Pin Input Pin CK, CK Input Pin CS Input Pin LDM, UDM Input Pin LDQS, UDQS Input/Output Pin DQ0-DQ15 Input/Output Pin NC RAS WE VDDQ VDD VREF VSSQ VSS -- Input Pin Input Pin Power Power Power Power Power Supply Supply Supply Supply Supply Pin Pin Pin Pin Pin Function (In Detail) Address inputs are sampled during several commands. During an Active command, A0-A12 select a row to open. During a Read or Write command, A0-A8 select a starting column for a burst. During a Pre-charge command, A10 determines whether all banks are to be pre-charged, or a single bank. During a Load Mode Register command, the address inputs select an operating mode. Bank Address inputs are used to select a bank during Active, Pre-charge, Read, or Write commands. During a Load Mode Register command, BA0 and BA1 are used to select between the Base or Extended Mode Register CAS is Column Access Strobe, which is an input to the device command along with RAS and WE. See "Command Truth Table" for details. Clock Enable: CKE High activates and CKE Low de-activates internal clock signals and input/output buffers. When CKE goes Low, it can allow Self Refresh, Pre-charge Power Down, and Active Power Down. CKE must be High during entire Read and Write accesses. Input buffers except CK, CK, and CKE are disabled during Power Down. CKE uses an SSTL 2 input, but will detect a LVCMOS Low level after VDD is applied. All address and command inputs are sampled on the rising edge of the clock input CK and the falling edge of the differential clock input CK. Output data is referenced from the crossings of CK and CK. The Chip Select input enables the Command Decoding block of the device. When CS is disabled, a NOP occurs. See "Command Truth Table" for details. Multiple DDR SDRAM devices can be managed with CS. These are the Data Mask inputs. During a Write operation, the Data Mask input allows masking of the data bus. DM is sampled on each edge of DQS. There are two Data Mask input pins for the x16 DDR SDRAM. Each input applies to DQ0-DQ7, or DQ8-DQ15. These are the Data Strobe inputs. The Data Strobe is used for data capture. During a Read operation, the DQS output signal from the device is edgealigned with valid data on the data bus. During a Write operation, the DQS input should be issued to the DDR SDRAM device when the input values on DQ inputs are stable. There are two Data Strobe pins for the x16 DDR SDRAM. Each of the two Data Strobe pins applies to DQ0-DQ7, or DQ8-DQ15. The pins DQ0 to DQ15 represent the data bus. For Write operations, the data bus is sampled on Data Strobe. For Read operations, the data bus is sampled on the crossings of CK and CK. No Connect: This pin should be left floating. These pins could be used for 256Mbit or higher density DDR SDRAM. RAS is Row Access Strobe, which is an input to the device command along with CAS and WE. See "Command Truth Table" for details. WE is Write Enable, which is an input to the device command along with RAS and CAS. See "Command Truth Table" for details. VDDQ is the output buffer power supply. VDD is the device power supply. VREF is the reference voltage for SSTL 2. VSSQ is the output buffer ground. VSS is the device ground. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 3 IS43R16160A Block Diagram ISSI 16M x 16 Column Addresses A0 - A8, AP, BA0, BA1 Row Addresses A0 - A12, BA0, BA1 (R) Column address counter Column address buffer Row address buffer Refresh Counter Row decoder Memory array Column decoder Sense amplifier & I(O) bus Row decoder Memory array Bank 1 Row decoder Memory array Bank 2 Row decoder Memory array Bank 3 Bank 0 Column decoder Sense amplifier & I(O) bus 8192 x 256 x32 bit 8192 x 256 x 32 bit Column decoder Sense amplifier & I(O) bus 8192 x 256 x 32 bit Column decoder Sense amplifier & I(O) bus 8192 x 256 x 32 bit Input buffer Output buffer Control logic & timing generator DQ0-DQ15 CKE DLL Strobe Gen. DM Rev. 00B 11/28/05 CK CK DQS Data Strobe Capacitance* TA = 0 to 70C, VCC = 2.5V 0.2V, VCC = 2.6V 0.1V for DDR400, f = 1 Mhz Input Capacitance BA0, BA1, CKE, CS, RAS, (CAS, A0-A11, WE) Input Capacitance (CK, CK) Data & DQS I/O Capacitance Input Capacitance (DM) Symbol Min Max Unit CINI CIN2 COUT CIN3 2 2 4 4 3.0 3.0 5 5.0 pF pF pF pF Operating temperature range ..................0 to 70 C Storage temperature range ................-55 to 150 C VDDSupply Voltage Relative to VSS.....-1V to +3.6V VDDQ Supply Voltage Relative to VSS ......................................................-1V to +3.6V VREF and Inputs Voltage Relative to VSS ......................................................-1V to +3.6V I/O Pins Voltage Relative to VSS ..........................................-0.5V to VDDQ+0.5V Power dissipation .......................................... 1.6 W Data out current (short circuit) ...................... 50 mA *Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* *Note: Capacitance is sampled and not 100% tested. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 CS CK, CK RAS CAS WE IS43R16160A Functional Description ISSI (R) Power-Up Sequence The following sequence is required for POWER UP. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. 2. Start clock and maintain stable condition for a minimum of 200us. 3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high. 4. Precharge all banks. 5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to all of the rest address pins, A1~A11 and BA1) 6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0) 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command to initialize device operation. Note1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. Power up Sequence & Auto Refresh(CBR) 0 CK, CK ** ** 2 Clock min. 2 Clock min. EMRS MRS DLL Reset precharge ALL Banks 1 2 3 4 5 6 7 8 9 10 ** 11 12 13 14 ** 15 16 17 18 19 tRP 1st Auto Refresh tRFC ** ** 2nd Auto Refresh tRFC ** ** 2 Clock min. Mode Register Set Any Command Command 200 S Power up to 1st command precharge ALL Banks min. 200 Cycle 4 5 6 7 8 8 The extended mode register stores the data for enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A12 and BA1 in the same cycle as CS, RAS, CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. A1 is used at EMRS to indicate I/O strength A1 = 0 full strength, A1 = 1 half strength. Refer to the table for specific codes. Extended Mode Register Set (EMRS) Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 5 IS43R16160A Mode Register Set (MRS) ISSI (R) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock cycles are required to meet tMRD spec. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a specific test mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. 1. MRS can be issued only at all banks precharge state. 2. Minimum tRP is required to issue MRS command. Address Bus BA1 BA 0 A12 to A3 A2 A1 A0 0 MRS RFU : Must be set "0" 0 I/O DLL Extended Mode Register Mode Register 0 MRS RFU DLL TM CAS Latency BT Burst Length A8 0 1 BA0 0 1 An ~ A0 DLL Reset No Yes A7 0 1 mode Normal Test A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 Reserve Reserve 2.5 Reserve A3 0 1 Burst Type Sequential Interleave Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A1 0 1 I/O Strength Full Half A0 0 1 DLL Enable Enable Disable CAS Latency A6 A5 0 0 0 0 1 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 0 0 1 1 0 0 1 1 (Existing)MRS Cycle Extended Funtions(EMRS) Latency Sequential Reserve 2 4 8 Reserve Reserve Reserve Reserve Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve Mode Register Set 0 CK, CK 1 2 3 *1 Mode Register Set 4 5 6 7 8 Command tCK Precharge All Banks Any Command tRP *2 tMRD 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Mode Register Set Timing T0 T1 tCK CK, CK Command Pre- All MRS/EMRS ANY ISSI T2 T3 tRP T4 T5 tMRD T6 T7 T8 T9 (R) Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state. If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command to allow time for the DLL to lock onto the clock. Burst Mode Operation Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and burst length. These parameters are programmable and are determined by address bits A0--A3 during the Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst length controls the number of bits that will be output after a Read command, or the number of bits to be input after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length and Sequence table below for programming information. Burst Length and Sequence Burst Length 2 Starting Length (A2, A1, A0) xx0 xx1 x00 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0,1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0,1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 4 x01 x10 x11 000 001 010 8 011 100 101 110 111 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 7 IS43R16160A ISSI (R) The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0 and BA1) are supported. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from the Bank Activate command to the first Read or Write command must meet or exceed the minimum RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Activate Command Bank Activation Timing (CAS Latency = 2; Burst Length = Any) T0 T1 T2 tRAS(min) tRCD(min) CK, CK BA/Address Command Bank/Row Activate/A Bank/Col Read/A Bank Pre/A Bank/Row Activate/A Bank/Row Activate/B T3 Tn tRC Tn+1 Tn+2 tRP(min) Tn+3 Tn+4 tRRD(min) Tn+5 Begin Precharge Bank A With the DLL enabled, all devices operating at the same frequency within a system are ensured to have the same timing relationship between DQ and DQS relative to the CK input regardless of device density, process variation, or technology generation. The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock frequency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and the system clock (CK) are all nominally aligned. Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed and used to latch the output data into the receiving device. The tolerance for skew between DQS and DQ (tDQSQ) is tighter than that possible for CK to DQ (tAC) or DQS to CK (tDQSCK). Read Operation 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK) During Read Cycles ISSI (CAS Latency = 2.5; Burst Length = 4) T1 T2 T3 T4 (R) T0 CK, CK Command READ NOP NOP NOP NOP tDQSCK(max) tDQSCK(min) DQS tAC(min) tAC(max) DQ D0 D1 D2 D3 The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a memory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (tDQSV) are derived from the minimum clock high/low time minus a margin for variation in data access and hold time due to DLL jitter and power supply noise. Read Preamble and Postamble Operation Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe "read preamble" (tRPRE). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of valid data. Once the burst of read data is concluded and given that no subsequent burst read operations are initiated, the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data strobe "read postamble" (tRPST). This transition happens nominally one-half clock period after the last edge of valid data. Consecutive or "gapless" burst read operations are possible from the same DDR SDRAM device with no requirement for a data strobe "read" preamble or postamble in between the groups of burst data. The data strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 9 IS43R16160A ISSI (CAS Latency = 2; Burst Length = 2) T0 T1 T2 T3 T4 (R) Data Strobe Preamble and Postamble Timings for DDR Read Cycles CK, CK Command READ NOP NOP tRPRE(max) NOP tRPRE(min) DQS tDQSQ(min) tRPST(min) tRPST(max) DQ D0 D1 tDQSQ(max) Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble Burst Read Operation (CAS Latency = 2; Burst Length = 4) CK, CK Command DQS DQ D0A D1A D2A D3A D0B D1B D2B D3B ReadA NOP ReadB NOP NOP NOP NOP NOP NOP Burst Read Operation (CAS Latency = 2; Burst Length = 4) CK, CK Command DQS DQ D0A D1A D2A D3A D0B D1B D2B D3B ReadA NOP NOP ReadB NOP NOP NOP NOP NOP 10 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Auto Precharge Operation ISSI (R) The Auto Precharge operation can be issued by having column address A10 high when a Read or Write command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. When the Auto Precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the Read or Write cycle once tRAS(min) is satisfied. Read with Auto Precharge If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency programmed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (tRP) has been satisfied. Read with Autoprecharge Timing (CAS Latency = 2; Burst Length = 4) T0 T1 T2 T3 tRAS(min) CK, CK Command DQS DQ D0 D1 D2 D3 ACT NOP R/w AP NOP NOP NOP NOP BA NOP T4 T5 T6 tRP(min) T7 T8 T9 Begin Autoprecharge Earliest Bank A reactivate Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 11 IS43R16160A ISSI Read with Autoprecharge Timing as a Function of CAS Latency (CAS Latency = 2, 2.5 Burst Length = 4) T1 T2 T3 T4 T5 T6 tRP(min) T7 T8 T9 (R) T0 tRAS(min) CK, CK Command BA NOP NOP RD AP NOP NOP NOP BA NOP NOP DQS DQ D0 D1 D2 D3 CAS Latency=2 DQS DQ D0 D1 D2 D3 CAS Latency=2.5 12 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI (R) Precharge Timing During Read Operation For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time (tRP). A Precharge command can not be issued until tRAS(min) is satisfied. Read with Precharge Timing as a Function of CAS Latency (CAS Latency = 2, 2.5; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 tRP(min) T7 T8 T9 tRAS(min) CK, CK Command BA NOP NOP Read NOP PreA NOP BA NOP NOP DQS DQ D0 D1 D2 D3 CAS Latency=2 DQS DQ D0 D1 D2 D3 CAS Latency=2.5 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 13 IS43R16160A ISSI (R) The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay (LBST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a burst Write cycle, the command will be treated as a NOP command. Burst Stop Command Read Terminated by Burst Stop Command Timing (CAS Latency = 2, 2.5; Burst Length = 2) T0 CK, CK Command Read LBST DQS CAS Latency = 2 DQ LBST DQS CAS Latency = 2.5 DQ D0 D1 D0 D1 BST NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 14 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Read Interrupted by a Precharge Timing (CAS Latency = 2, 2.5; Burst Length = 4) (R) Read Interrupted by a Precharge A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to Output Disable latency is equivalent to the CAS latency. T0 T1 T2 T3 T4 T5 T6 tRP(min) T7 T8 T9 tRAS(min) CK, CK Command BA NOP NOP Read NOP PreA NOP BA NOP NOP DQS DQ D0 D1 D2 D3 CAS Latency=2 DQS DQ D0 D1 D2 D3 CAS Latency=2.5 Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. The memory controller is required to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be driven high nominally one clock after the write command has been registered. Timing parameters tDQSS(min) and tDQSS(max) define the allowable window when the data strobe must be driven high. Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is registered into the device (WL=1). The input data valid window is nominally centered around the midpoint of the data strobe signal. The data window is defined by DQ to DQS setup time (tQDQSS) and DQ to DQS hold time (tQDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Write Preamble and Postamble Operation Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe "write preamble". This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write command has been registered by the device. The preamble is explicitly defined by a setup time (tWPRES(min)) and hold time (tWPREH(min)) referenced to the first falling edge of CK after the write command. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 15 IS43R16160A ISSI Burst Write Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 (R) CK, CK Command WRITE NOP NOP NOP tWPST tWPRES DQS(nom) tDQSS tDH tDS tDS tDH DQ(nom) D0 D1 D2 D3 tWPRES(min) DQS(min) tDQSS(min) DQ(min) D0 D1 D2 D3 tWPRES DQS(max) tDQSS(max) DQ(max) D0 D1 D2 D3 Once the burst of write data is concluded and given that no subsequent burst write operations are initiated, Once the burst of write data is concluded and given that no subsequent burst write operations are initiated, the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data strobe "write postamble". This transition happens nominally one-half clock period after the last data of the burst cycle is latched into the device. 16 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Write Interrupted by a Precharge Timing (CAS Latency = 2; Burst Length = 8) (R) Write Interrupted by a Precharge A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only restriction being that the interval that separates the commands be at least one clock cycle. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK, CK Command DQS DQ DM D0 D1 D2 D3 D4 D5 D6 WriteA NOP NOP PreA NOP tWR NOP NOP NOP NOP NOP NOP Data is masked by DM input Data is masked by Precharge Command DQS input ignored Write with Auto Precharge If A10 is high when a Write command is issued, the Write with auto Precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR (min.). Write with Auto Precharge Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 tRAS(min) CK, CK Command BA NOP NOP WAP NOP NOP NOP NOP NOP NOP BA DQS tWR(min) DQ D0 D1 D2 D3 tRP(min) Begin Autoprecharge Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 17 IS43R16160A Precharge Timing During Write Operation ISSI (R) Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery requirement. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The "write recovery" operation begins on the rising clock edge after the last DQS edge that is used to strobe in the last valid write data. "Write recovery" is complete on the next 2nd rising clock edge that is used to strobe in the Precharge command. Write with Precharge Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tRP(min) T10 tRAS(min) CK, CK Command BA NOP NOP Write NOP NOP NOP NOP tWR DQS DQ D0 D1 D2 D3 tWR DQS DQ D0 D1 D2 D3 PreA NOP BA 18 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Data Mask Function ISSI Data Mask Timing (CAS Latency = Any; Burst Length = 8) (R) The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask to Data Latency = 0). When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe. T0 CK, CK Command T1 T2 T3 T4 T5 T6 T7 T8 T9 Write tDS NOP NOP NOP NOP NOP tDS NOP NOP DQS tDH DQ D0 D1 D2 D3 D4 D5 D6 D7 tDH DM Burst Interruption Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears on the bus. Read commands can be issued on each rising edge of the system clock. It is illegal to interrupt a Read with autoprecharge command with a Read command. Read Interrupted by a Read Command Timing (CAS Latency = 2; Burst Length = 4) T0 CK, CK Command DQS DQ DA0 DA1 DB0 DB1 DB2 DB3 ReadA ReadB NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 19 IS43R16160A ISSI (R) Read Interrupted by a Write To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or latency (LBST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half clock cycles, the minimum delay (LBST) is rounded up to the next full clock cycle (i.e., if CL=2 then LBST=2, if CL=2.5 then LBST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command. Read Interrupted by Burst Stop Command Followed by a Write Command Timing (CAS Latency = 2; Burst Length = 4) T0 CK, CK Command DQS DQ D0 LBST D1 D0 D1 D2 D3 Read BST NOP Write NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 Write Interrupted by a Write A Burst Write can be interrupted before completion by a new Write command to any bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. The data from the first Write command continues to be input into the device until the Write Latency of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write command is input into the device. Write commands can be issued on each rising edge of the system clock. It is illegal to interrupt a Write with autoprecharge command with a Write command. Write Interrupted by a Write Command Timing (CAS Latency = Any; Burst Length = 4) T0 CK, CK Command DQS DQ DM DA0 DA1 DB0 DB1 DB2 DB3 DM0 DM1 DM0 DM1 DM2 DM3 Write Latency WriteA WriteB NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 20 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI (R) Write Interrupted by a Read A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory array. Any data that is present on the DQ pins coincident with or following the Read command will be masked off by the Read command and will not be written to the array. The memory controller must give up control of both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in order to avoid contention. In order to avoid data contention within the device, a delay is required (tWTR) from the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write with autoprecharge command with a Read command. Write Interrupted by a Read Command Timing (CAS Latency = 2; Burst Length = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK, CK Command DQS DQ DM D0 D1 D2 D3 D4 D5 D0 D 1 D 2 D3 D4 D 5 D 6 D7 Write NOP NOP tWTR Read NOP NOP NOP NOP NOP NOP NOP Data is masked by DM input Data is masked by Read command DQS input ignored The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the rising edge of the clock. All banks must be precharged and idle for a tRP(min) before the Auto Refresh command is applied. No control of the address pins is required once this cycle has started because of the internal address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate command or subsequent Auto Refresh command must be greater than or equal to the tRFC(min). Commands may not be issued to the device once an Auto Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be registered on each rising edge of the CK input until the refresh period is satisfied. Auto Refresh Auto Refresh Timing T0 T1 T2 tRP T3 T4 T5 T6 T7 tRFC T8 T9 T10 T11 CK, CK Command Pre All Auto Ref NOP NOP NOP ANY CKE High Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 21 IS43R16160A ISSI (R) A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tSREX for locking of DLL. The auto refresh is required before self refresh entry and after self refresh exit. Self Refresh CK, CK Command CKE Self Refresh ** ** ** Stable Clock NOP ** ** ** Auto Refresh ** tSREX Power Down Mode The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tck+tIS prior to row active command. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (tREF) of the device. CK, CK ** ** Command Precharge Precharge power down Entry precharge ** power down Exit Active ** NOP Read CKE ** ** Active power down Entry Active power down Exit 22 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A TRUTH TABLE 2 - CKE (Notes: 1-4) ISSI CURRENT STATE Power-Down (R) CKEn-1 CKEn COMMANDn X X ACTIONn Maintain Power-Down Maintain Self Refresh NOTES L L Self Refresh Power-Down L H Self Refresh DESELECT or NOP DESELECT or NOP Exit Power-Down Exit Self Refresh 5 All Banks Idle H L Bank(s) Active All Banks Idle H H DESELECT or NOP DESELECT or NOP AUTO REFRESH See Truth Table 3 Precharge Power-Down Entry Active Power-Down Entry Self Refresh Entry NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 200 clock cycles is needed before applying a read command, for the DLL to lock. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 23 IS43R16160A DDR SDRAM SIMPLIFIED COMMAND TRUTH TABLE Command Mode Register Set Extended Mode Register Set ISSI CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X ADDR A10/ AP OP code OP code (R) BA Note 1,2 1,2 1 Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit X V V 1 1 1,3 1 1,4 1,5 1 1 1 1 H X L H L L CA V X V H H H H L X X H L H L L L L H L H L H L H L L H L L X H X H X H X V X H H L L X H X H X H X V L L H H X H X H X H X V X X 1 1 Entry Precharge Power Down Mode Exit H L X 1 1 1 1 L H Active Power Down Mode Entry Exit H L L H X 1 1 ( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. 24 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A TRUTH TABLE 3 - Current State Bank n - Command to Bank n (Notes: 1-6; notes appear below and on next page) ISSI /CS H L L (R) CURRENT STATE Any /RAS X H L L L H H L H L H H H L /CAS X H H L L L L H L H H L L H /WE X H H H L H L L H L L H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) AUTO REFRESH MODE REGISTER SET READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) PRECHARGE (truncate READ burst, start PRECHARGE) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate WRITE burst, start PRECHARGE) NOTES Idle L L L 7 7 10 10 8 10 8 9 10, 11 10 8, 11 Row Active L L L Read (Auto Precharge Disabled) L L L Write (Auto Precharge Disabled) L L NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 25 IS43R16160A ISSI Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the "row active" state. (R) NOTE: (continued) Read w/Auto-Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRFC is met, the DDR SDRAM will be in the "all banks idle" state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the "all banks idle" state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle and no bursts are in progress. 8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank. 10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 11. Requires appropriate DM masking. 26 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A TRUTH TABLE 4 - Current State Bank n - Command to Bank m (Notes: 1-6; notes appear below and on next page) ISSI /CS H L X L (R) CURRENT STATE Any Idle /RAS /CAS /WE X H X L H H L L H L L H H L L H H L L H H L X H X H L L H H L H H L L H H L L H H L L H X H X H H L L H H L H H L L H H L L H H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE NOTES Row Activating, Active, or Precharging L L L 7 7 Read (Auto-Precharge Disabled) L L L L 7 Write (Auto- Precharge Disabled) L L L L 7, 8 7 Read (With Auto-Precharge) L L L L 3a, 7 3a, 7, 9 Write (With Auto-Precharge) L L L 3a, 7 3a, 7 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 27 IS43R16160A ISSI (R) NOTE: (continued) Read with Auto Precharge Enabled: See following text Write with Auto Precharge Enabled: See following text 3a. The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided). 4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 8. Requires appropriate DM masking. 9. A WRITE command may be applied after the completion of data output. 28 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Simplified State Diagram Power Applied Power On ISSI (R) Precharge PREALL REFS REFSX MRS EMRS MRS REFA Auto Refresh Self Refresh Idle CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL Write Write Write A Write Row Active Burst Stop Read Read Read A Read Read Write A Read A Write A PRE PRE PRE Read A Read A Precharge PRE PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 29 IS43R16160A DC Operating Conditions & Specifications DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C) ISSI (R) Parameter Supply voltage (for device with a nominal VDD of 2.5V) Supply voltage (VDD of 2.6V for DDR400 device) I/O Supply voltage I/O Supply voltage for DDR400 device I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input leakage current Output leakage current Output High Current (VOUT = 1.95V) Output Low Current (VOUT = 0.35V) Symbol VDD VDD VDDQ VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) II IOZ IOH IOL Min 2.3 2.5 2.3 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 -2 -5 -16.8 16.8 Max 2.7 2.7 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 2 5 Unit Note V V V V V V V V uA uA mA mA 3 1 2 Notes: 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed 2% of the DC value 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 30 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Version Conditions Symbol -5 -6 Unit (R) IDD Max Specifications and Conditions (0C < TA < 70C, VDDQ=2.5V+ 0.2V, VDD=2.5 +0.2V, for DDR400 device VDDQ=2.6V+ 0.1V, VDD=2.6 +0.1V) Operating current - One bank Active-Precharge; tRC=tRCmin;tCK= tCK (min); DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation; One bank open, BL=4 Precharge power-down standby current; All banks idle; power - down mode; CKE = IDD2F 52 45 mA IDD2Q 50 44 mA IDD3P 30 25 mA IDD3N 90 270 80 230 mA IDD4R mA IDD4W 250 210 mA Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 31 IS43R16160A AC Operating Conditions & Timing Specification AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs ISSI Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 (R) Min VREF + 0.31 Max Unit V Note 1 2 3 4 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 V V V Note: 1.Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD. 2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS. 3. VID is the magnitude of the difference between the input level on CK and the input on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. ELECTRICAL CHARACTERISTICS AND AC TIMING for PC400/PC333/PC266 -Absolute Specifications (Notes: 1-5, 14-17) (0C < T A < 70C; VDDQ = +2.5V 0.2V, VDD=+2.5V 0.2V for DDR400 device VDDQ = +2.6V 0.1V, VDD=+2.6V 0.1V) AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK CK high-level width CK low-level width Clock cycle time CL = 3 CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS t -5 SYMBOL t -6 MAX 0.65 0.55 0.55 10 10 10 MIN -0.65 0.45 0.45 5 6 7.5 0.40 0.40 1.75 -0.6 MIN -0.7 0.45 0.45 6 6 7.5 0.45 0.45 1.75 MAX 0.7 0.55 0.55 12 12 12 UNITS ns tCK t NOTES AC tCH t 30 30 52 52 52 26,31 26,31 31 CL CK ns CK (3) (2.5) tCK t ns ns ns ns ns CK (2) t DH DS t DQ and DM input pulse width (for each in- t DIPW put) Access window of DQS from CK/CK DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access t DQSCK t 0.6 -0.6 0.35 0.35 0.6 t ns CK DQSH 0.35 0.35 0.40 0.72 0.2 0.2 1.25 tDQSL t tCK DQSQ 0.45 0.75 0.2 0.2 1.25 t t t ns CK CK CK 25,26 Write command to first DQS latching tran- t DQSS sition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time t t DSS DSH 32 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI -5 SYMBOL t (R) AC CHARACTERISTICS PARAMETER Half clock period Data-out high-impedance window from CK/CK Data-out low-impedance window from CK/CK Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window t t t -6 MIN t MIN t MAX MAX UNITS ns NOTES 34 18 18 14 14 14 14 HP CH, t CL +0.65 +0.65 CH, t CL +0.7 +0.7 tHZ -0.65 -0.65 0.60 0.60 0.70 0.70 2 t HP -tQHS -0.7 -0.7 0.75 0.75 0.80 0.80 2 t HP -tQHS ns ns ns ns ns ns tCK t LZ t IHF tIS F t IHS ISS t tMRD tQH ns 0.55 ns ns ns ns ns ns ns 1.1 0.6 tCK t 25, 26 QHS 40 15 60 70 15 15 0.9 0.4 10 0.25 0 0.4 15 2 t 0.50 70,000 42 18 60 72 18 18 1.1 0.6 0.9 0.4 12 0.25 0 0.6 0.4 15 1 t t tRAS 120,000 35 46 t RAP t RC tRFC t 50 RCD t RP tRPRE t 42 RPST t CK ns RRD tWPRE tCK WPRES t ns 0.6 t 20, 21 19 WPST tWR CK ns WTR na t t CK ns 25 QH - DQSQ QH - DQSQ Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 33 IS43R16160A ISSI -5 SYMBOL t (R) AC CHARACTERISTICS PARAMETER Average periodic refresh interval Terminating voltage delay to VDD -6 MAX 7.8 MIN MIN MAX 7.8 UNITS NOTES us ns ns tCK REFI 0 75 200 tVTD 0 75 200 Exit SELF REFRESH to non-READ com- t XSNR mand Exit SELF REFRESH to READ command tXSRD 34 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI (R) SLEW RATE DERATING VALUES (Notes: 14) 0C TA +70C; VDDQ= +2.5V 0.2V, VDD = +2.5V 0.2V for DDR400 VDDQ= +2.6V 0.1V, VDD = +2.6V 0.1V ADDRESS / COMMAND SLEW RATE 0.500V / ns 0.400V / ns 0.300V / ns 0.200V / ns tIS 0 +50 +100 +150 tIH 0 +50 +100 +150 UNITS ps ps ps ps NOTES 14 14 14 14 SLEW RATE DERATING VALUES (Note: 31) 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V for DDR400 VDDQ= +2.6V 0.1V, VDD = +2.6V 0.1V Data, DQS, DM SLEW RATE 0.500V / ns 0.400V / ns 0.300V / ns 0.200V / ns tDS 0 +75 +150 +225 tDH 0 +75 +150 +225 UNITS ps ps ps ps NOTES 31 31 31 31 NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: VTT 50 Output (VOUT) Reference Point 30pF Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 35 IS43R16160A NOTES: (continued) ISSI (R) 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmit-ting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK. 9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -6 with the outputs open. 11. Enables on-chip refresh and address counters. 12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, T A = 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. Command/Address input slew rate = 0.5V/ns. For -5 and -6 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS and tIH has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VDDQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 36 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A NOTES: (continued) 23. The refresh period 64ms. This equates to an average refresh rate of 7.8s. ISSI (R) 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device.. 30. CK and CK input slew rate must be > 1V/ns. 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4% if CKE is not active while any bank is active. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 37 IS43R16160A NOTES: (continued) ISSI (R) 33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 36. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid. Initial JEDEC specifications suggested this to be same as tDQSQ. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 V. 39. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. 42. Note 42 is not used. 38 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A NOTES: (continued) 43. Note 43 is not used. ISSI (R) 44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 45. Note 45 is not used. 46. tRAP > t RCD. 47. Note 47 is not used. 48. Random addressing changing 50% of data changing at every transfer. 49. Random addressing changing 100% of data changing at every transfer. 50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 80 70 60 50 40 30 20 10 0 0.0 gh Nominal hi 0 Max imum -20 Minimum Nominal low -40 Nominal low -60 Nom inal Minimum -80 hig h -100 Ma xim um 2.5 -120 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 39 IS43R16160A ISSI (R) IBIS: I/V Characteristics for Input and Output Buffers Normal strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 160 Maximum 140 Iout(mA) 120 Typical High 100 80 60 Typical Low Minimum 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 Vout(V) 3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure b. 0.0 0 0.5 1.0 1.5 2.0 2.5 Minumum Typical Low Iout(mA) -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 Typical High Maximum VDDQ Vout(V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2 40 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Pulldown Current (mA) Pullup Current (mA) Maximum 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Typical Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -41.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Typical High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Minimum -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Maximum -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2 Typical High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Minimum 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 (R) Figure 25. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Typical Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Table 17. Pull down and pull up current values Temperature (Tambient) Typical 25C Minimum 70C Maximum 0C Vdd/Vddq Typical Minimum Maximum DDR333/DDR266 2.5V 2.3V 2.7V DDR400 2.6V 2.5V 2.7V The above characteristics are specified under best, worst and normal process variation/conditions Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 41 IS43R16160A Half strength driver ISSI (R) 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 90 80 70 60 Maximum Typical High Typical Low Minimum Iout(mA) Iout(mA) 40 30 20 10 0 0.0 1.0 2.0 50 Vout(V) 3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure b. 0.0 0 0.5 1.0 1.5 2.0 2.5 -10 -20 Iout(mA) -30 Minumum Typical Low -40 -50 -60 Typical High -70 -80 Maximum -90 VDDQ Vout(V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2 42 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Pulldown Current (mA) Pullup Current (mA) Maximum 5.0 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7 Typical Low -3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9 Typical High -4.3 -8.2 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8 Minimum -2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3 Maximum -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7 Typical High 3.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6 Minimum 2.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6 (R) Figure 26. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Typical Low 3.4 6.9 10.3 13.6 16.9 19.6 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8 Table 18. Pull down and pull up current values Temperature (Tambient) Typical 25C Minimum 70C Maximum 0C Vdd/Vddq DDR333/DDR266 Typical 2.5V Minimum 2.3V Maximum 2.7V DDR400 2.6V 2.5V 2.7V Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 43 IS43R16160A The above characteristics are specified under best, worst and normal process variation/conditions ISSI Figure 36 - DATA INPUT (WRITE) TIMING tDSL DQS tDSH (R) tDS DI n DQ tDH tDS DM tDH DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n Figure 37 - DATA OUTPUT (READ) TIMING tDQSQ max t DQSQ nom tDQSQ max DQS DQ tDQSQ min tDQSQ min 1. tDQSQ max occurs when DQS is the earliest among DQS and DQ signals to transition. 2. tDQSQ min occurs when DQS is the latest among DQS and DQ signals to transition. 3. tDQSQ nom, shown for reference, occurs when DQS transitions in the center among DQ signal transitions. DQS, DQ tDV Burst Length = 4 in the case shown 44 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Figure 38 - INITIALIZE AND MODE REGISTER SETS (R) VDD VDDQ VTT (system*) VREF t VTD tCK tCH /CK CK (( )) (( )) tCL (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) t IS t IH CKE LVCMOS LOW LEVEL (( )) tIS tIH PRE EMRS (( )) (( )) (( )) (( )) COMMAND NOP (( )) (( )) (( )) (( )) MRS PRE AR AR MRS ACT DM tIS A0-A9, A11 (( )) (( )) (( )) (( )) (( )) (( )) tIH CODE (( )) (( )) (( )) (( )) CODE (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) CODE RA ALL BANKS tIS tIH ALL BANKS A10 CODE CODE (( )) (( )) (( )) (( )) tIS tIH tIS tIH (( )) (( )) tIS BA0=L, BA1=L (( )) (( )) tIH (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) CODE RA BA0, BA1 BA0=H, BA1=L BA0=L, BA1=L BA DQS DQ (( )) (( )) T = 200s High-Z (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) High-Z t MRD Power-up: VDD and CLK stable Extended Mode Register Set t MRD t RP t RFC t RFC t MRD 200 cycles of CLK** Load Mode Register (with A8 = L) DON'T CARE Load Mode Register, Reset DLL (with A8 = H) * = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up. ** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied. The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 45 IS43R16160A Figure 39 - POWER-DOWN MODE tCK /CK CK tIS tIH CKE tIS COMMAND tIH NOP ISSI tCH tCL (( )) (( )) (R) tIS tIS (( )) VALID* tIS ADDR tIH (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) NOP VALID VALID VALID DQS DQ DM Enter Power-Down Mode Exit Power-Down Mode DON'T CARE No column accesses are allowed to be in progress at the time Power-Down is entered * = If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active) then the Power-Down mode shown is Active Power Down. 46 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Figure 40 - AUTO REFRESH MODE tCK tCH tCL (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) ALL BANKS (R) /CK CK CKE tIS COMMAND tIH PRE NOP NOP AR tIS tIH VALID (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) VALID NOP NOP AR NOP NOP ACT A0-A8 RA A9, A11 RA A10 ONE BANK (( )) (( )) RA tIS BA0, BA1 tIH (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) *Bank(s) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA DQS DQ DM t RP t RC t RC DON'T CARE * = "Don't Care", if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e. must precharge all active banks) PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other valid commands may be possible at these times DM, DQ and DQS signals are all "Don't Care"/High-Z for operations shown Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 47 IS43R16160A Figure 41 - SELF REFRESH MODE tCK tCH /CK CK tIS tIH CKE tIS COMMAND tIH AR ISSI tCL clock must be stable before exiting Self Refresh mode (( )) (( )) (( )) (( )) (( )) (( )) (R) tIS tIS NOP (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) NOP (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) VALID tIS tIH ADDR VALID DQS DQ DM tRP* Enter Self Refresh Mode tXSNR/ tXSRD** Exit Self Refresh Mode DON'T CARE * = Device must be in the "All banks idle" state prior to entering Self Refresh mode ** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CLK) are required before a READ command can be applied. 48 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Figure 42 - READ - WITHOUT AUTO PRECHARGE tCK /CK CK CKE tIS COMMAND tIH READ NOP ISSI tCH tCL tIH (R) tIS tIH Start! Autoprecharge PRE NOP NOP ACT VALID VALID VALID NOP NOP NOP NOP tIS A0-A7 tIH RA Col n A8, A9, A11 tIS A10 DIS AP ONE BANK RA tIH ALL BANKS RA tIS BA0, BA1 tIH *Bank x Bank x Bank x CL = 2 DM Case 1: tAC/tDQSCK = min tRP t DQSCK min tRPRE DQS tLZ min tLZ min Case 2: tAC/tDQSCK = max tHZ min tAC min tRPST DQ DO n tRPRE DQS tLZ max tLZ max t DQSCK max tRPST DQ DO n tHZ max t AC max DON'T CARE DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 49 IS43R16160A Figure 43 - READ - WITH AUTO PRECHARGE tCK /CK CK CKE tIS COMMAND tIH READ NOP PRE NOP NOP ACT NOP NOP ISSI tCH tCL tIS tIH tIH VALID VALID VALID (R) NOP NOP tIS A0-A7 tIH RA Col n A8, A9, A11 tIS A10 DIS AP ONE BANK RA tIH ALL BANKS RA tIS BA0, BA1 tIH *Bank x Bank x Bank x CL = 2 DM Case 1: tAC/tDQSCK = min tRP t DQSCK min tRPRE DQS tLZ min tLZ min Case 2: tAC/tDQSCK = max tHZ min tAC min tRPST DQ DO n tRPRE DQS tLZ max tLZ max t DQSCK max tRPST DQ DO n tHZ max t AC max DON'T CARE DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times 50 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Figure 44 - BANK READ ACCESS tCK /CK CK CKE tIS COMMAND tIH ACT NOP NOP NOP READ NOP PRE NOP NOP ISSI tCH tCL (R) tIS tIH NOP ACT tIS A0-A7 RA tIH Col n RA A8, A9, A11 RA RA tIS A10 RA tIH ALL BANKS RA DIS AP ONE BANK tIS BA0, BA1 tIH Bank x *Bank x Bank x Bank x tRC tRAS tRCD CL = 2 tRP DM Case 1: tAC/tDQSCK = min t DQSCK min tRPRE DQS tLZ min tLZ min Case 2: tAC/tDQSCK = max tHZ min tAC min tRPST DQ DO n tRPRE DQS tLZ max tLZ max t DQSCK max tRPST DQ DO n tHZ max t AC max DON'T CARE DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting) Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 51 IS43R16160A Figure 45 - WRITE - WITHOUT AUTO PRECHARGE tCK /CK CK CKE tIS COMMAND tIH WRITE NOP NOP NOP NOP PRE NOP NOP ISSI tCH tCL tIS tIH tIH VALID (R) NOP ACT tIS A0-A7 tIH RA Col n A8, A9, A11 tIS A10 DIS AP ONE BANK RA tIH ALL BANKS RA tIS BA0, BA1 tIH *Bank x BA Bank x tRP Case 1: tDQSS = min tDQSS DQS tWPRES tWPRE DI n tDSH tDQSH tDSH tWR tWPST tDQSL DQ DM Case 2: tDQSS = max tDQSS DQS tWPRES tWPRE tDSS tDQSH tDSS tWPST tDQSL DQ DI n DM DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times 52 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A Figure 46 - WRITE - WITH AUTO PRECHARGE tCK /CK CK CKE tIS COMMAND tIH WRITE NOP NOP NOP NOP NOP NOP NOP ISSI tCH tCL tIH VALID VALID VALID (R) tIS NOP ACT tIS A0-A7 tIH RA Col n A8, A9, A11 EN AP RA A10 tIS BA0, BA1 tIH RA Bank x BA tDAL Case 1: tDQSS = min tDQSS DQS tWPRES tWPRE DI n tDSH tDQSH tDSH tWPST tDQSL DQ DM Case 2: tDQSS = max tDQSS DQS tWPRES tWPRE tDSS tDQSH tDSS tWPST tDQSL DQ DI n DM DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 53 IS43R16160A Figure 47 - BANK WRITE ACCESS tCK /CK CK CKE tIS COMMAND tIH ACT NOP NOP WRITE NOP NOP NOP NOP ISSI tCH tCL tIS tIH (R) NOP PRE tIS A0-A7 RA tIH Col n A8, A9, A11 RA tIS A10 RA tIH ALL BANKS DIS AP ONE BANK tIS BA0, BA1 tIH Bank x *Bank x Bank x tRAS tRCD Case 1: tDQSS = min tDQSS DQS tWPRES tWPRE DI n tWR tDSH tDQSH tDSH tWPST tDQSL DQ DM Case 2: tDQSS = max tDQSS DQS tWPRES tWPRE tDSS tDQSH tDSS tWPST tDQSL DQ DI n DM DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times 54 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 IS43R16160A ISSI Order Part No. IS43R16160A-5T IS43R16160A-5TL IS43R16160A-6T Package 66-pin TSOP-II 66-pin TSOP-II, Lead-free 66-pin TSOP-II (R) ORDERING INFORMATION Commercial Range: 0C to +70C Frequency 200 MHz 200 MHz 166 MHz Speed (ns) 5 5 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00B 11/28/05 55 PACKAGING INFORMATION Plastic TSOP 66-pin Package Code: T (Type II) ISSI N/2+1 E1 E Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be (R) N measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 1 D N/2 SEATING PLANE ZD A e b L A1 C Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 66 A A1 A2 b C D E1 E e L L1 ZD -- 1.20 0.05 0.15 -- -- 0.24 0.40 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.65 BSC 0.40 0.60 -- -- 0.71 REF 0 8 -- 0.047 0.002 0.006 -- -- 0.009 0.016 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.026 BSC 0.016 0.024 -- -- 0.028 REF 0 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 08/09/05 1 |
Price & Availability of IS43R16160A-6T
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |